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dyncom: Support conditional BKPT instructions

This commit is contained in:
Lioncash 2015-02-17 01:31:36 -05:00
parent 012d1e32ad
commit a7120662e6
2 changed files with 28 additions and 2 deletions
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2
src/core/arm/dyncom/arm_dyncom_dec.cpp
View File

@ -42,7 +42,7 @@ const ISEITEM arm_instruction[] = {
{ "srs", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005 }, { "srs", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000001, 16, 20, 0x0000000d, 8, 11, 0x00000005 },
{ "rfe", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a }, { "rfe", 4, 6, 25, 31, 0x0000007c, 22, 22, 0x00000000, 20, 20, 0x00000001, 8, 11, 0x0000000a },
{ "bkpt", 2, 3, 20, 31, 0x00000e12, 4, 7, 0x00000007 }, { "bkpt", 2, 3, 20, 27, 0x00000012, 4, 7, 0x00000007 },
{ "blx", 1, 3, 25, 31, 0x0000007d }, { "blx", 1, 3, 25, 31, 0x0000007d },
{ "cps", 3, 6, 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000 }, { "cps", 3, 6, 20, 31, 0x00000f10, 16, 16, 0x00000000, 5, 5, 0x00000000 },
{ "pld", 4, 4, 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f }, { "pld", 4, 4, 26, 31, 0x0000003d, 24, 24, 0x00000001, 20, 22, 0x00000005, 12, 15, 0x0000000f },

28
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View File

@ -792,6 +792,7 @@ typedef struct _stm_inst {
} stm_inst; } stm_inst;
struct bkpt_inst { struct bkpt_inst {
u32 imm;
}; };
struct blx1_inst { struct blx1_inst {
@ -1371,7 +1372,22 @@ static ARM_INST_PTR INTERPRETER_TRANSLATE(bic)(unsigned int inst, int index)
inst_base->br = INDIRECT_BRANCH; inst_base->br = INDIRECT_BRANCH;
return inst_base; return inst_base;
} }
static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index) { UNIMPLEMENTED_INSTRUCTION("BKPT"); }
static ARM_INST_PTR INTERPRETER_TRANSLATE(bkpt)(unsigned int inst, int index)
{
arm_inst* const inst_base = (arm_inst*)AllocBuffer(sizeof(arm_inst) + sizeof(bkpt_inst));
bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
inst_base->cond = BITS(inst, 28, 31);
inst_base->idx = index;
inst_base->br = NON_BRANCH;
inst_base->load_r15 = 0;
inst_cream->imm = BITS(inst, 8, 19) | BITS(inst, 0, 3);
return inst_base;
}
static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index) static ARM_INST_PTR INTERPRETER_TRANSLATE(blx)(unsigned int inst, int index)
{ {
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst)); arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(blx_inst));
@ -4081,6 +4097,16 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
GOTO_NEXT_INST; GOTO_NEXT_INST;
} }
BKPT_INST: BKPT_INST:
{
if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) {
bkpt_inst* const inst_cream = (bkpt_inst*)inst_base->component;
LOG_DEBUG(Core_ARM11, "Breakpoint instruction hit. Immediate: 0x%08X", inst_cream->imm);
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC(sizeof(bkpt_inst));
FETCH_INST;
GOTO_NEXT_INST;
}
BLX_INST: BLX_INST:
{ {
blx_inst *inst_cream = (blx_inst *)inst_base->component; blx_inst *inst_cream = (blx_inst *)inst_base->component;