170 lines
5.0 KiB
C++
170 lines
5.0 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <optional>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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namespace Tegra {
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namespace Engines {
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class Maxwell3D;
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}
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class MacroInterpreter final {
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public:
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explicit MacroInterpreter(Engines::Maxwell3D& maxwell3d);
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/**
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* Executes the macro code with the specified input parameters.
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* @param offset Offset to start execution at.
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* @param parameters The parameters of the macro.
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*/
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void Execute(u32 offset, std::vector<u32> parameters);
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private:
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enum class Operation : u32 {
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ALU = 0,
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AddImmediate = 1,
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ExtractInsert = 2,
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ExtractShiftLeftImmediate = 3,
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ExtractShiftLeftRegister = 4,
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Read = 5,
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Unused = 6, // This operation doesn't seem to be a valid encoding.
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Branch = 7,
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};
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enum class ALUOperation : u32 {
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Add = 0,
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AddWithCarry = 1,
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Subtract = 2,
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SubtractWithBorrow = 3,
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// Operations 4-7 don't seem to be valid encodings.
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Xor = 8,
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Or = 9,
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And = 10,
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AndNot = 11,
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Nand = 12
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};
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enum class ResultOperation : u32 {
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IgnoreAndFetch = 0,
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Move = 1,
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MoveAndSetMethod = 2,
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FetchAndSend = 3,
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MoveAndSend = 4,
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FetchAndSetMethod = 5,
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MoveAndSetMethodFetchAndSend = 6,
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MoveAndSetMethodSend = 7
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};
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enum class BranchCondition : u32 {
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Zero = 0,
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NotZero = 1,
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};
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union Opcode {
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u32 raw;
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BitField<0, 3, Operation> operation;
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BitField<4, 3, ResultOperation> result_operation;
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BitField<4, 1, BranchCondition> branch_condition;
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BitField<5, 1, u32>
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branch_annul; // If set on a branch, then the branch doesn't have a delay slot.
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BitField<7, 1, u32> is_exit;
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BitField<8, 3, u32> dst;
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BitField<11, 3, u32> src_a;
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BitField<14, 3, u32> src_b;
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// The signed immediate overlaps the second source operand and the alu operation.
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BitField<14, 18, s32> immediate;
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BitField<17, 5, ALUOperation> alu_operation;
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// Bitfield instructions data
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BitField<17, 5, u32> bf_src_bit;
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BitField<22, 5, u32> bf_size;
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BitField<27, 5, u32> bf_dst_bit;
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u32 GetBitfieldMask() const {
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return (1 << bf_size) - 1;
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}
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s32 GetBranchTarget() const {
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return static_cast<s32>(immediate * sizeof(u32));
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}
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};
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union MethodAddress {
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u32 raw;
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BitField<0, 12, u32> address;
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BitField<12, 6, u32> increment;
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};
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/// Resets the execution engine state, zeroing registers, etc.
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void Reset();
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/**
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* Executes a single macro instruction located at the current program counter. Returns whether
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* the interpreter should keep running.
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* @param offset Offset to start execution at.
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* @param is_delay_slot Whether the current step is being executed due to a delay slot in a
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* previous instruction.
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*/
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bool Step(u32 offset, bool is_delay_slot);
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/// Calculates the result of an ALU operation. src_a OP src_b;
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u32 GetALUResult(ALUOperation operation, u32 src_a, u32 src_b) const;
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/// Performs the result operation on the input result and stores it in the specified register
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/// (if necessary).
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void ProcessResult(ResultOperation operation, u32 reg, u32 result);
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/// Evaluates the branch condition and returns whether the branch should be taken or not.
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bool EvaluateBranchCondition(BranchCondition cond, u32 value) const;
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/// Reads an opcode at the current program counter location.
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Opcode GetOpcode(u32 offset) const;
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/// Returns the specified register's value. Register 0 is hardcoded to always return 0.
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u32 GetRegister(u32 register_id) const;
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/// Sets the register to the input value.
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void SetRegister(u32 register_id, u32 value);
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/// Sets the method address to use for the next Send instruction.
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void SetMethodAddress(u32 address);
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/// Calls a GPU Engine method with the input parameter.
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void Send(u32 value);
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/// Reads a GPU register located at the method address.
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u32 Read(u32 method) const;
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/// Returns the next parameter in the parameter queue.
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u32 FetchParameter();
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Engines::Maxwell3D& maxwell3d;
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u32 pc; ///< Current program counter
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std::optional<u32>
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delayed_pc; ///< Program counter to execute at after the delay slot is executed.
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static constexpr std::size_t NumMacroRegisters = 8;
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/// General purpose macro registers.
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std::array<u32, NumMacroRegisters> registers = {};
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/// Method address to use for the next Send instruction.
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MethodAddress method_address = {};
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/// Input parameters of the current macro.
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std::vector<u32> parameters;
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/// Index of the next parameter that will be fetched by the 'parm' instruction.
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u32 next_parameter_index = 0;
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};
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} // namespace Tegra
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