Merge pull request #245 from Subv/set_shader2
GPU: Store shader constbuffer bindings in the GPU state.
This commit is contained in:
commit
29981fa2eb
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@ -15,6 +15,7 @@ const std::unordered_map<u32, Maxwell3D::MethodInfo> Maxwell3D::method_handlers
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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void Maxwell3D::CallMethod(u32 method, const std::vector<u32>& parameters) {
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void Maxwell3D::CallMethod(u32 method, const std::vector<u32>& parameters) {
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// TODO(Subv): Write an interpreter for the macros uploaded via registers 0x45 and 0x47
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auto itr = method_handlers.find(method);
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auto itr = method_handlers.find(method);
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if (itr == method_handlers.end()) {
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if (itr == method_handlers.end()) {
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LOG_ERROR(HW_GPU, "Unhandled method call %08X", method);
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LOG_ERROR(HW_GPU, "Unhandled method call %08X", method);
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@ -42,6 +43,26 @@ void Maxwell3D::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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ASSERT_MSG(regs.code_address.CodeAddress() == 0, "Unexpected CODE_ADDRESS register value.");
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break;
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break;
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}
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}
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case MAXWELL3D_REG_INDEX(cb_bind[0].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Vertex);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[1].raw_config): {
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ProcessCBBind(Regs::ShaderStage::TesselationControl);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[2].raw_config): {
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ProcessCBBind(Regs::ShaderStage::TesselationEval);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[3].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Geometry);
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break;
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}
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case MAXWELL3D_REG_INDEX(cb_bind[4].raw_config): {
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ProcessCBBind(Regs::ShaderStage::Fragment);
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break;
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}
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case MAXWELL3D_REG_INDEX(draw.vertex_end_gl): {
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case MAXWELL3D_REG_INDEX(draw.vertex_end_gl): {
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DrawArrays();
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DrawArrays();
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break;
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break;
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@ -83,22 +104,54 @@ void Maxwell3D::SetShader(const std::vector<u32>& parameters) {
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/**
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/**
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* Parameters description:
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* Parameters description:
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* [0] = Shader Program.
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* [0] = Shader Program.
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* [1] = Unknown.
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* [1] = Unknown, presumably the shader id.
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* [2] = Offset to the start of the shader, after the 0x30 bytes header.
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* [2] = Offset to the start of the shader, after the 0x30 bytes header.
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* [3] = Shader Type.
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* [3] = Shader Stage.
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* [4] = Shader End Address >> 8.
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* [4] = Const Buffer Address >> 8.
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*/
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*/
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auto shader_program = static_cast<Regs::ShaderProgram>(parameters[0]);
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auto shader_program = static_cast<Regs::ShaderProgram>(parameters[0]);
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// TODO(Subv): This address is probably an offset from the CODE_ADDRESS register.
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// TODO(Subv): This address is probably an offset from the CODE_ADDRESS register.
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GPUVAddr begin_address = parameters[2];
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GPUVAddr address = parameters[2];
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auto shader_type = static_cast<Regs::ShaderType>(parameters[3]);
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auto shader_stage = static_cast<Regs::ShaderStage>(parameters[3]);
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GPUVAddr end_address = parameters[4] << 8;
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GPUVAddr cb_address = parameters[4] << 8;
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auto& shader = state.shaders[static_cast<size_t>(shader_program)];
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auto& shader = state.shader_programs[static_cast<size_t>(shader_program)];
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shader.program = shader_program;
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shader.program = shader_program;
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shader.type = shader_type;
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shader.stage = shader_stage;
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shader.begin_address = begin_address;
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shader.address = address;
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shader.end_address = end_address;
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// Perform the same operations as the real macro code.
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// TODO(Subv): Early exit if register 0xD1C + shader_program contains the same as params[1].
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auto& shader_regs = regs.shader_config[static_cast<size_t>(shader_program)];
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shader_regs.start_id = address;
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// TODO(Subv): Write params[1] to register 0xD1C + shader_program.
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// TODO(Subv): Write params[2] to register 0xD22 + shader_program.
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// Note: This value is hardcoded in the macro's code.
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static constexpr u32 DefaultCBSize = 0x10000;
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regs.const_buffer.cb_size = DefaultCBSize;
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regs.const_buffer.cb_address_high = cb_address >> 32;
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regs.const_buffer.cb_address_low = cb_address & 0xFFFFFFFF;
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// Write a hardcoded 0x11 to CB_BIND, this binds the current const buffer to buffer c1[] in the
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// shader. It's likely that these are the constants for the shader.
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regs.cb_bind[static_cast<size_t>(shader_stage)].valid.Assign(1);
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regs.cb_bind[static_cast<size_t>(shader_stage)].index.Assign(1);
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ProcessCBBind(shader_stage);
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}
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void Maxwell3D::ProcessCBBind(Regs::ShaderStage stage) {
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// Bind the buffer currently in CB_ADDRESS to the specified index in the desired shader stage.
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auto& shader = state.shader_stages[static_cast<size_t>(stage)];
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auto& bind_data = regs.cb_bind[static_cast<size_t>(stage)];
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auto& buffer = shader.const_buffers[bind_data.index];
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buffer.enabled = bind_data.valid.Value() != 0;
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buffer.index = bind_data.index;
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buffer.address = regs.const_buffer.BufferAddress();
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buffer.size = regs.const_buffer.cb_size;
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}
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}
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} // namespace Engines
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} // namespace Engines
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@ -35,8 +35,12 @@ public:
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struct Regs {
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struct Regs {
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static constexpr size_t NUM_REGS = 0xE36;
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static constexpr size_t NUM_REGS = 0xE36;
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static constexpr size_t NumCBData = 16;
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t NumVertexArrays = 32;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderProgram = 6;
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static constexpr size_t MaxShaderStage = 5;
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// Maximum number of const buffers per shader stage.
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static constexpr size_t MaxConstBuffers = 16;
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enum class QueryMode : u32 {
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enum class QueryMode : u32 {
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Write = 0,
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Write = 0,
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@ -52,7 +56,7 @@ public:
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Fragment = 5,
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Fragment = 5,
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};
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};
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enum class ShaderType : u32 {
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enum class ShaderStage : u32 {
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Vertex = 0,
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Vertex = 0,
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TesselationControl = 1,
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TesselationControl = 1,
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TesselationEval = 2,
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TesselationEval = 2,
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@ -132,17 +136,37 @@ public:
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u32 start_id;
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u32 start_id;
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INSERT_PADDING_WORDS(1);
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INSERT_PADDING_WORDS(1);
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u32 gpr_alloc;
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u32 gpr_alloc;
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ShaderType type;
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ShaderStage type;
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INSERT_PADDING_WORDS(9);
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INSERT_PADDING_WORDS(9);
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} shader_config[MaxShaderProgram];
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} shader_config[MaxShaderProgram];
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INSERT_PADDING_WORDS(0x5D0);
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INSERT_PADDING_WORDS(0x8C);
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struct {
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struct {
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u32 shader_code_call;
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u32 cb_size;
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u32 shader_code_args;
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u32 cb_address_high;
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} shader_code;
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u32 cb_address_low;
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u32 cb_pos;
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u32 cb_data[NumCBData];
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GPUVAddr BufferAddress() const {
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return static_cast<GPUVAddr>(
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(static_cast<GPUVAddr>(cb_address_high) << 32) | cb_address_low);
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}
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} const_buffer;
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INSERT_PADDING_WORDS(0x10);
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INSERT_PADDING_WORDS(0x10);
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struct {
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union {
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u32 raw_config;
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BitField<0, 1, u32> valid;
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BitField<4, 5, u32> index;
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};
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INSERT_PADDING_WORDS(7);
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} cb_bind[MaxShaderStage];
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INSERT_PADDING_WORDS(0x50A);
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};
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};
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std::array<u32, NUM_REGS> reg_array;
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std::array<u32, NUM_REGS> reg_array;
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};
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};
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@ -151,17 +175,28 @@ public:
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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struct State {
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struct State {
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struct ShaderInfo {
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struct ConstBufferInfo {
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Regs::ShaderType type;
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GPUVAddr address;
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u32 index;
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u32 size;
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bool enabled;
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};
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struct ShaderProgramInfo {
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Regs::ShaderStage stage;
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Regs::ShaderProgram program;
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Regs::ShaderProgram program;
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GPUVAddr begin_address;
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GPUVAddr address;
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GPUVAddr end_address;
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};
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};
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std::array<ShaderInfo, Regs::MaxShaderProgram> shaders;
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struct ShaderStageInfo {
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std::array<ConstBufferInfo, Regs::MaxConstBuffers> const_buffers;
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};
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};
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State state;
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std::array<ShaderStageInfo, Regs::MaxShaderStage> shader_stages;
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std::array<ShaderProgramInfo, Regs::MaxShaderProgram> shader_programs;
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};
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State state{};
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private:
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private:
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MemoryManager& memory_manager;
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MemoryManager& memory_manager;
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@ -169,6 +204,9 @@ private:
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/// Handles a write to the QUERY_GET register.
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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void ProcessQueryGet();
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/// Handles a write to the CB_BIND register.
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void ProcessCBBind(Regs::ShaderStage stage);
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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/// Handles a write to the VERTEX_END_GL register, triggering a draw.
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void DrawArrays();
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void DrawArrays();
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@ -194,7 +232,8 @@ ASSERT_REG_POSITION(query, 0x6C0);
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ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(shader_code, 0xE24);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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#undef ASSERT_REG_POSITION
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#undef ASSERT_REG_POSITION
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