384 lines
7.1 KiB
C
384 lines
7.1 KiB
C
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//===== Copyright <20> 1996-2005, Valve Corporation, All rights reserved. ======//
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//
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// Purpose:
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//
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// $NoKeywords: $
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//
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//===========================================================================//
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#ifndef IA32DETECT_H
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#define IA32DETECT_H
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#ifdef COMPILER_MSVC64
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extern "C" void __cpuid(int* CPUInfo, int InfoType);
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#pragma intrinsic (__cpuid)
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#endif
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/*
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This section from http://iss.cs.cornell.edu/ia32.htm
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*/
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typedef unsigned bit;
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enum CPUVendor
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{
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INTEL,
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AMD,
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UNKNOWN_VENDOR
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};
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class ia32detect
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{
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public:
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enum type_t
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{
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type_OEM,
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type_OverDrive,
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type_Dual,
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type_reserved
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};
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enum brand_t
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{
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brand_na,
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brand_Celeron,
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brand_PentiumIII,
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brand_PentiumIIIXeon,
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brand_reserved1,
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brand_reserved2,
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brand_PentiumIIIMobile,
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brand_reserved3,
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brand_Pentium4,
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brand_invalid
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};
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# pragma pack(push, 1)
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struct version_t
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{
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bit Stepping : 4;
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bit Model : 4;
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bit Family : 4;
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bit Type : 2;
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bit Reserved1 : 2;
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bit XModel : 4;
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bit XFamily : 8;
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bit Reserved2 : 4;
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};
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struct misc_t
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{
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byte Brand;
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byte CLFLUSH;
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byte Reserved;
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byte APICId;
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};
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struct feature_t
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{
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bit FPU : 1; // Floating Point Unit On-Chip
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bit VME : 1; // Virtual 8086 Mode Enhancements
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bit DE : 1; // Debugging Extensions
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bit PSE : 1; // Page Size Extensions
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bit TSC : 1; // Time Stamp Counter
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bit MSR : 1; // Model Specific Registers
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bit PAE : 1; // Physical Address Extension
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bit MCE : 1; // Machine Check Exception
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bit CX8 : 1; // CMPXCHG8 Instruction
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bit APIC : 1; // APIC On-Chip
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bit Reserved1 : 1;
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bit SEP : 1; // SYSENTER and SYSEXIT instructions
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bit MTRR : 1; // Memory Type Range Registers
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bit PGE : 1; // PTE Global Bit
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bit MCA : 1; // Machine Check Architecture
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bit CMOV : 1; // Conditional Move Instructions
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bit PAT : 1; // Page Attribute Table
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bit PSE36 : 1; // 32-bit Page Size Extension
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bit PSN : 1; // Processor Serial Number
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bit CLFSH : 1; // CLFLUSH Instruction
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bit Reserved2 : 1;
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bit DS : 1; // Debug Store
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bit ACPI : 1; // Thermal Monitor and Software Controlled Clock Facilities
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bit MMX : 1; // Intel MMX Technology
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bit FXSR : 1; // FXSAVE and FXRSTOR Instructions
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bit SSE : 1; // Intel SSE Technology
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bit SSE2 : 1; // Intel SSE2 Technology
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bit SS : 1; // Self Snoop
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bit HTT : 1; // Hyper Threading
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bit TM : 1; // Thermal Monitor
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bit Reserved3 : 1;
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bit PBE : 1; // Pending Brk. EN.
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};
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# pragma pack(pop)
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tstring vendor_name;
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CPUVendor vendor;
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tstring brand;
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version_t version;
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misc_t misc;
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feature_t feature;
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byte *cache;
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ia32detect ()
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{
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cache = 0;
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uint32 m = init0();
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uint32 *d = new uint32[m * 4];
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for (uint32 i = 1; i <= m; i++)
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{
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#ifdef COMPILER_MSVC64
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__cpuid((int *) (d + (i-1) * 4), i);
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#else
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uint32 *t = d + (i - 1) * 4;
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__asm
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{
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mov eax, i;
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mov esi, t;
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cpuid;
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mov dword ptr [esi + 0x0], eax;
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mov dword ptr [esi + 0x4], ebx;
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mov dword ptr [esi + 0x8], ecx;
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mov dword ptr [esi + 0xC], edx;
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}
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#endif
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}
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if (m >= 1)
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init1(d);
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if (m >= 2)
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init2(d[4] & 0xFF);
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delete [] d;
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init0x80000000();
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//-----------------------------------------------------------------------
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// Get the vendor of the processor
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//-----------------------------------------------------------------------
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if (_tcscmp(vendor_name.c_str(), _T("GenuineIntel")) == 0)
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{
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vendor = INTEL;
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}
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else if (_tcscmp(vendor_name.c_str(), _T("AuthenticAMD")) == 0)
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{
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vendor = AMD;
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}
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else
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{
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vendor = UNKNOWN_VENDOR;
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}
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}
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const tstring version_text () const
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{
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tchar b[128];
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_stprintf(b, _T("%d.%d.%d %s XVersion(%d.%d)"),
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version.Family, version.Model, version.Stepping, type_text(), version.XFamily, version.XModel);
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return tstring(b);
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}
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protected:
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const tchar * type_text () const
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{
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static const tchar *text[] =
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{
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_T("Intel OEM Processor"),
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_T("Intel OverDrive(R) Processor"),
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_T("Intel Dual Processor"),
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_T("reserved")
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};
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return text[version.Type];
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}
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const tstring brand_text () const
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{
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static const tchar *text[] =
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{
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_T("n/a"),
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_T("Celeron"),
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_T("Pentium III"),
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_T("Pentium III Xeon"),
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_T("reserved (4)"),
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_T("reserved (5)"),
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_T("Pentium III Mobile"),
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_T("reserved (7)"),
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_T("Pentium 4")
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};
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if (misc.Brand < brand_invalid)
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return tstring(text[misc.Brand]);
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else
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{
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tchar b[32];
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_stprintf(b, _T("Brand %d (Update)"), misc.Brand);
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return tstring(b);
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}
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}
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private:
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uint32 init0 ()
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{
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uint32 m;
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#ifdef COMPILER_MSVC64
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int data[4];
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tchar * s1;
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s1 = (tchar *) &data[1];
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s1[12] = '\0';
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__cpuid(data, 0);
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m = data[0];
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vendor_name = s1;
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#else
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tchar s1[13];
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s1[12] = '\0';
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__asm
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{
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xor eax, eax;
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cpuid;
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mov m, eax;
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mov dword ptr s1 + 0, ebx;
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mov dword ptr s1 + 4, edx;
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mov dword ptr s1 + 8, ecx;
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}
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vendor_name = s1;
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#endif
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return m;
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}
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void init1 (uint32 *d)
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{
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version = *(version_t *)&d[0];
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misc = *(misc_t *)&d[1];
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feature = *(feature_t *)&d[3];
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}
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void process2 (uint32 d, bool c[])
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{
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if ((d & 0x80000000) == 0)
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for (int i = 0; i < 32; i += 8)
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c[(d >> i) & 0xFF] = true;
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}
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void init2 (byte count)
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{
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uint32 d[4];
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bool c[256];
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for (int ci1 = 0; ci1 < 256; ci1++)
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c[ci1] = false;
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for (int i = 0; i < count; i++)
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{
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#ifdef COMPILER_MSVC64
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__cpuid((int *) d, 2);
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#else
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__asm
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{
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mov eax, 2;
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lea esi, d;
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cpuid;
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mov [esi + 0x0], eax;
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mov [esi + 0x4], ebx;
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mov [esi + 0x8], ecx;
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mov [esi + 0xC], edx;
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}
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#endif
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if (i == 0)
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d[0] &= 0xFFFFFF00;
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process2(d[0], c);
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process2(d[1], c);
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process2(d[2], c);
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process2(d[3], c);
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}
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int m = 0;
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for (int ci2 = 0; ci2 < 256; ci2++)
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if (c[ci2])
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m++;
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cache = new byte[m];
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m = 0;
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for (int ci3 = 1; ci3 < 256; ci3++)
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if (c[ci3])
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cache[m++] = ci3;
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cache[m] = 0;
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}
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void init0x80000000 ()
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{
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uint32 m;
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#ifdef COMPILER_MSVC64
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int data[4];
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__cpuid(data, 0x80000000);
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m = data[0];
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#else
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__asm
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{
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mov eax, 0x80000000;
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cpuid;
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mov m, eax
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}
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#endif
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if ((m & 0x80000000) != 0)
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{
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uint32 *d = new uint32[(m - 0x80000000) * 4];
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for (uint32 i = 0x80000001; i <= m; i++)
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{
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uint32 *t = d + (i - 0x80000001) * 4;
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#ifdef COMPILER_MSVC64
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__cpuid((int *) (d + (i - 0x80000001) * 4), i);
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#else
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__asm
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{
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mov eax, i;
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mov esi, t;
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cpuid;
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mov dword ptr [esi + 0x0], eax;
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mov dword ptr [esi + 0x4], ebx;
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mov dword ptr [esi + 0x8], ecx;
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mov dword ptr [esi + 0xC], edx;
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}
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#endif
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}
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if (m >= 0x80000002)
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brand = (tchar *)(d + 4);
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// note the assignment to brand above does a copy, we need to delete
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delete[] d;
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}
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}
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};
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#endif // IA32DETECT_H
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